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Ninth Asian Test Symposium (ATS'00)
Testing programmable interconnect systems: an algorithmic approach
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
ASCII Text
x 
 
B. Liu, F. Lombardi, W.K. Huang, "Testing programmable interconnect systems: an algorithmic approach," Asian Test Symposium, pp. 311, Ninth Asian Test Symposium (ATS'00), 2000.
 
 
BibTex
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@article{ 10.1109/ATS.2000.893642,
author = {B. Liu and F. Lombardi and W.K. Huang},
title = {Testing programmable interconnect systems: an algorithmic approach},
journal ={Asian Test Symposium},
volume = {0},
year = {2000},
issn = {1081-7735},
pages = {311},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893642},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Testing programmable interconnect systems: an algorithmic approach
SN - 1081-7735
SP
EP
A1 - B. Liu,
A1 - F. Lombardi,
A1 - W.K. Huang,
PY - 2000
KW - programmable circuits; circuit testing; circuit analysis computing; fault diagnosis; interconnected systems; interconnections; automatic test software; programmable interconnect systems testing; algorithmic approach; fault detection; programmable wiring networks; comprehensive fault model; network faults; open faults; stuck-at faults; short circuits; switch faults; stuck-off faults; stuck-on faults; programming faults; figure of merit; programming phases; minimal configuration number; graphs; node-disjoint path-sets; switching; network adjacencies; bridge faults; fault coverage; post-processing algorithm
VL - 0
JA - Asian Test Symposium
ER -
 
B. Liu, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W.K. Huang, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Presents an approach for fault detection in programmable wiring networks (PWNs). A comprehensive fault model which includes faults in the nets (open, stuck-at and shorts) as well as in the switches (stuck-off, stuck-on and programming faults) is assumed at both the physical and behavioral levels. In a PWN, the most important issue is to find the minimal number of configurations (or programming phases) as the dominant figure of merit of testing. Through the construction of different graphs, it is shown that this process corresponds to finding the node-disjoint path-sets such that each switch is turned on/off at least once and adjacencies in the nets for possible bridge faults (shorts) are verified. To account for 100% fault coverage of bridge faults, a post-processing algorithm may be required.
Index Terms:
programmable circuits; circuit testing; circuit analysis computing; fault diagnosis; interconnected systems; interconnections; automatic test software; programmable interconnect systems testing; algorithmic approach; fault detection; programmable wiring networks; comprehensive fault model; network faults; open faults; stuck-at faults; short circuits; switch faults; stuck-off faults; stuck-on faults; programming faults; figure of merit; programming phases; minimal configuration number; graphs; node-disjoint path-sets; switching; network adjacencies; bridge faults; fault coverage; post-processing algorithm
Citation:
B. Liu, F. Lombardi, W.K. Huang, "Testing programmable interconnect systems: an algorithmic approach," ats, pp.311, Ninth Asian Test Symposium (ATS'00), 2000
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