Ninth Asian Test Symposium (ATS'00) Detection of SRAM cell stability by lowering array supply voltage Taipei, Taiwan December 04-December 06 ISBN: 0-7695-0887-1
In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability.
Index Terms:
CMOS memory circuits; SRAM chips; circuit stability; design for testability; integrated circuit testing; logic testing; SRAM cell stability detection; array supply voltage reduction; design-for-test technique; DFT technique; static random access memory; memory array; CMOS technology; test mode; detection capability; 0.18 micron
Citation:
Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou, "Detection of SRAM cell stability by lowering array supply voltage," ats, pp.268, Ninth Asian Test Symposium (ATS'00), 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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