A BIST methodology for at-speed testing of data communications transceivers

A
ATS
2000
Ninth Asian Test Symposium (ATS'00)
Abstract - A BIST methodology for at-speed testing of data communications transceivers

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S.L. Lin Articles by S. Mourad Articles by S. Krishnan

Ninth Asian Test Symposium (ATS'00)

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	S.L. Lin, S. Mourad, S. Krishnan, "A BIST methodology for at-speed testing of data communications transceivers," Asian Test Symposium, pp. 216, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893628, author = {S.L. Lin and S. Mourad and S. Krishnan}, title = {A BIST methodology for at-speed testing of data communications transceivers}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {216}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893628}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A BIST methodology for at-speed testing of data communications transceivers SN - 1081-7735 SP EP A1 - S.L. Lin, A1 - S. Mourad, A1 - S. Krishnan, PY - 2000 KW - data communication equipment; transceivers; built-in self test; telecommunication equipment testing; integrated circuit testing; automatic testing; CMOS integrated circuits; BIST methodology; at-speed testing; data communications transceivers; functional testing; data communications chip; 3-port IEEE 1394a system; CMOS implementation; 0.35 micron; 400 Mbit/s VL - 0 JA - Asian Test Symposium ER -

S.L. Lin, Intelligent Micro Inc., San Jose, CA, USA

S. Mourad, Intelligent Micro Inc., San Jose, CA, USA

S. Krishnan, Intelligent Micro Inc., San Jose, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893628

This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.

Index Terms:

data communication equipment; transceivers; built-in self test; telecommunication equipment testing; integrated circuit testing; automatic testing; CMOS integrated circuits; BIST methodology; at-speed testing; data communications transceivers; functional testing; data communications chip; 3-port IEEE 1394a system; CMOS implementation; 0.35 micron; 400 Mbit/s

Citation:

S.L. Lin, S. Mourad, S. Krishnan, "A BIST methodology for at-speed testing of data communications transceivers," ats, pp.216, Ninth Asian Test Symposium (ATS'00), 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.