T. Masuzawa, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
M. Izutsu, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Wada, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Fujiwara, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
This paper presents a new BIST method for RTL data paths based on single-control testability a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses, paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single stuck-at faults), low hardware overhead and capability of at-speed testing. Moreover test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at the speed of the system clock.
Index Terms:
built-in self test; logic testing; integrated circuit testing; automatic test pattern generation; design for testability; VLSI; digital integrated circuits; single-control testability; RTL data paths; BIST method; hierarchical test; test pattern generators; response analyzers; DFT method; high fault coverage; single stuck-at faults; low hardware overhead; at-speed testing; transition faults; delay faults; ATPG; VLSI circuits
Citation:
T. Masuzawa, M. Izutsu, H. Wada, H. Fujiwara, "Single-control testability of RTL data paths for BIST," ats, pp.210, Ninth Asian Test Symposium (ATS'00), 2000