In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. This paper discusses how fault coverage can be improved with a short test pattern that repeatedly samples an R number of instructions as L sets from an S number of instructions and selects from amongst these L sets those for which the fault coverage can be improved. Continuing, it argues that the processing speed can be increased by selecting a certain number of sets containing an R number of instructions from an S number of instructions. This approach proved effective in tests using software created on these principles.
Index Terms:
microprocessor chips; automatic test pattern generation; instruction sets; integrated circuit testing; logic testing; identification; microprocessor functional ATPG; microprocessor tests; instruction sets; fault coverage improvement; short test pattern; processing speed increase; functional testing; test pattern generation
Citation:
J. Hirase, S. Yoshimura, "Faster processing for microprocessor functional ATPG," ats, pp.191, Ninth Asian Test Symposium (ATS'00), 2000
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