Fast hierarchical test path construction for DFT-free controller-datapath circuits

A
ATS
2000
Ninth Asian Test Symposium (ATS'00)
Abstract - Fast hierarchical test path construction for DFT-free controller-datapath circuits

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Ninth Asian Test Symposium (ATS'00)

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	Y. Makris, J. Collins, A. Orailoglu, "Fast hierarchical test path construction for DFT-free controller-datapath circuits," Asian Test Symposium, pp. 185, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893623, author = {Y. Makris and J. Collins and A. Orailoglu}, title = {Fast hierarchical test path construction for DFT-free controller-datapath circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {185}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893623}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Fast hierarchical test path construction for DFT-free controller-datapath circuits SN - 1081-7735 SP EP A1 - Y. Makris, A1 - J. Collins, A1 - A. Orailoglu, PY - 2000 KW - automatic test pattern generation; logic testing; fast hierarchical test path construction; DFT-free controller-datapath circuits; transparency based scheme; locally generated vectors; global design test; influence tables; valid control state sequences; module testing; fault coverage levels; vector counts; test generation; computational cost reduction; ATPG VL - 0 JA - Asian Test Symposium ER -

Y. Makris, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

J. Collins, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893623

We discuss a hierarchical test generation method for DFT-free controller-datapath pairs. A transparency based scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. The controller is examined through influence tables, used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage levels and vector counts thus attained match closely, those of traditional test generation methodologies, while sharply reducing the corresponding computational cost.

Index Terms:

automatic test pattern generation; logic testing; fast hierarchical test path construction; DFT-free controller-datapath circuits; transparency based scheme; locally generated vectors; global design test; influence tables; valid control state sequences; module testing; fault coverage levels; vector counts; test generation; computational cost reduction; ATPG

Citation:

Y. Makris, J. Collins, A. Orailoglu, "Fast hierarchical test path construction for DFT-free controller-datapath circuits," ats, pp.185, Ninth Asian Test Symposium (ATS'00), 2000

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