Forecasting the efficiency of test generation algorithms for digital circuits

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Shiyi Xu Articles by Wei Cen

Ninth Asian Test Symposium (ATS'00)

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	Shiyi Xu, Wei Cen, "Forecasting the efficiency of test generation algorithms for digital circuits," Asian Test Symposium, pp. 179, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893622, author = {Shiyi Xu and Wei Cen}, title = {Forecasting the efficiency of test generation algorithms for digital circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {179}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893622}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Forecasting the efficiency of test generation algorithms for digital circuits SN - 1081-7735 SP EP A1 - Shiyi Xu, A1 - Wei Cen, PY - 2000 KW - integrated circuit testing; VLSI; genetic algorithms; digital integrated circuits; sequential circuits; combinational circuits; logic testing; automatic test pattern generation; test generation algorithms; efficiency forecasting; digital circuits; VLSI circuits; testability parameters; combinational circuits; sequential circuits; genetic algorithms; ATPG VL - 0 JA - Asian Test Symposium ER -

Shiyi Xu, Sch. of Comput. Sci. & Eng., Shanghai Univ., China

Wei Cen, Sch. of Comput. Sci. & Eng., Shanghai Univ., China

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893622

Within this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to confirm the validity and usefulness of this approach.

Index Terms:

integrated circuit testing; VLSI; genetic algorithms; digital integrated circuits; sequential circuits; combinational circuits; logic testing; automatic test pattern generation; test generation algorithms; efficiency forecasting; digital circuits; VLSI circuits; testability parameters; combinational circuits; sequential circuits; genetic algorithms; ATPG

Citation:

Shiyi Xu, Wei Cen, "Forecasting the efficiency of test generation algorithms for digital circuits," ats, pp.179, Ninth Asian Test Symposium (ATS'00), 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.