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Ninth Asian Test Symposium (ATS'00)
Fault diagnosis for linear analog circuits
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
Jun-Weir Lin, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung-Len Lee, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chau-Chin Su, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu-E Chen, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.
Index Terms:
fault diagnosis; analogue circuits; signal flow graphs; linear analog circuits; discrete signal flow graph; equivalent faults; fault diagnosis
Citation:
Jun-Weir Lin, Chung-Len Lee, Chau-Chin Su, Jwu-E Chen, "Fault diagnosis for linear analog circuits," ats, pp.25, Ninth Asian Test Symposium (ATS'00), 2000
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