Ninth Asian Test Symposium (ATS'00) Current status and future trend on CAD tools for VLSI testing Taipei, Taiwan December 04-December 06 ISBN: 0-7695-0887-1
For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort.
Index Terms:
integrated circuit design; circuit CAD; automatic test pattern generation; VLSI; logic testing; built-in self test; integrated circuit economics; CAD; VLSI testing; VLSI design; embedded memories; BIST; automatic test pattern generation; ATPG; test logic; system on chip; SoC; deep Sub-Micron technologies; scan-based ATPG; test quality; test application cost; test development
Citation:
Wu-Tung Cheng, "Current status and future trend on CAD tools for VLSI testing," ats, pp.10, Ninth Asian Test Symposium (ATS'00), 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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