DFT and BIST techniques for the future

A
ATS
2000
Ninth Asian Test Symposium (ATS'00)
Abstract - DFT and BIST techniques for the future

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	Similar Articles Articles by Hsin-Po Wang Articles by J. Turino

Ninth Asian Test Symposium (ATS'00)

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	Hsin-Po Wang, J. Turino, "DFT and BIST techniques for the future," Asian Test Symposium, pp. 6, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893591, author = {Hsin-Po Wang and J. Turino}, title = {DFT and BIST techniques for the future}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {6}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893591}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - DFT and BIST techniques for the future SN - 1081-7735 SP EP A1 - Hsin-Po Wang, A1 - J. Turino, PY - 2000 KW - built-in self test; logic testing; design for testability; production testing; integrated circuit economics; DFT; BIST; multimillion gate system-on-chip; multinational design; time to market; integrated circuit design; quality; economics; IC design VL - 0 JA - Asian Test Symposium ER -

Hsin-Po Wang, SynTest Technols. Inc., Taiwan

J. Turino, SynTest Technols. Inc., Taiwan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893591

In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times.

Index Terms:

built-in self test; logic testing; design for testability; production testing; integrated circuit economics; DFT; BIST; multimillion gate system-on-chip; multinational design; time to market; integrated circuit design; quality; economics; IC design

Citation:

Hsin-Po Wang, J. Turino, "DFT and BIST techniques for the future," ats, pp.6, Ninth Asian Test Symposium (ATS'00), 2000

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