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Eighth Asian Test Symposium (ATS'99)
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
ASCII Text
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Lan Zhao, D.M.H. Walker, Fabrizio Lombardi, "IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs," Asian Test Symposium, pp. 375, Eighth Asian Test Symposium (ATS'99), 1999.
 
 
BibTex
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@article{ 10.1109/ATS.1999.810778,
author = {Lan Zhao and D.M.H. Walker and Fabrizio Lombardi},
title = {IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs},
journal ={Asian Test Symposium},
volume = {0},
year = {1999},
issn = {1081-7735},
pages = {375},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810778},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs
SN - 1081-7735
SP
EP
A1 - Lan Zhao,
A1 - D.M.H. Walker,
A1 - Fabrizio Lombardi,
PY - 1999
VL - 0
JA - Asian Test Symposium
ER -
 
Lan Zhao, Lucent Technologies
D.M.H. Walker, Texas A&M University
Fabrizio Lombardi, Northeastern University
This paper presents a quiescent current-based (IDDQ) approach for testing input/output resources in SRAM-based FPGAs. Input/output resources include input/output blocks (IOBs) and the I/O interconnect. Test generation and application strategies are proposed by taking into account the limited controllability of the I/O resources. Configuration of these resources requires that the test stimuli must be provided by internal (logic and routing) resources. A detailed presentation for testing the I/O resources of the Xilinx XC4000 family is given.
Citation:
Lan Zhao, D.M.H. Walker, Fabrizio Lombardi, "IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs," ats, pp.375, Eighth Asian Test Symposium (ATS'99), 1999
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