Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs

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	Similar Articles Articles by Yinlei Yu Articles by Jian Xu Articles by Wei Kang Huang Articles by Fabrizio Lombardi

Eighth Asian Test Symposium (ATS'99)

Shanghai, China

November 16-November 18

ISBN: 0-7695-0315-2

	ASCII Text	x
	Yinlei Yu, Jian Xu, Wei Kang Huang, Fabrizio Lombardi, "Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs," Asian Test Symposium, pp. 357, Eighth Asian Test Symposium (ATS'99), 1999.

	BibTex	x
	@article{ 10.1109/ATS.1999.810775, author = {Yinlei Yu and Jian Xu and Wei Kang Huang and Fabrizio Lombardi}, title = {Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs}, journal ={Asian Test Symposium}, volume = {0}, year = {1999}, issn = {1081-7735}, pages = {357}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810775}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs SN - 1081-7735 SP EP A1 - Yinlei Yu, A1 - Jian Xu, A1 - Wei Kang Huang, A1 - Fabrizio Lombardi, PY - 1999 KW - FPGA KW - Fault Detection KW - Fault Diagnosis VL - 0 JA - Asian Test Symposium ER -

Yinlei Yu, Fudan University

Jian Xu, Fudan University

Wei Kang Huang, Fudan University

Fabrizio Lombardi, Northeastern University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810775

This paper presents a procedure to diagnose single faults in SRAM Based FPGAs. The procedure is non-adaptive and requires six programming steps to give the ex-act position and type of any single fault in a FPGA. It is proved that the number of programming steps required for the procedure is minimal for a non-adaptive procedure with the given interconnect model.

Index Terms:

FPGA, Fault Detection, Fault Diagnosis

Citation:

Yinlei Yu, Jian Xu, Wei Kang Huang, Fabrizio Lombardi, "Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs," ats, pp.357, Eighth Asian Test Symposium (ATS'99), 1999

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