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Eighth Asian Test Symposium (ATS'99)
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
Hiroshi Takahashi, Ehime University
Kwame Osei Boateng, Ehime University
Yuzo Takamatsu, Ehime University
Nobuhiro Yanagida, Kaminomoto Corporation
In this paper, we propose a method that uses EB tester and multiple/single fault simulators to diagnose multiple stuck-at faults in combinational circuits. Based on the primary output values and selected internal line values which are calculated by multiple/single fault simulators, faults are added to or removed from a set of suspected faults. The proposed method repeats additions and removals of faults to avoid missing actual faults in a faulty circuit. In order to reduce the number of lines to be probed by EB tester, the proposed method selects internal lines to be probed by using a backward path tracing procedure. The experimental results show that the proposed method achieves a small number of suspected faults by probing a small number of internal lines.
Index Terms:
fault diagnosis, combinational circuit, multiple stuck-at fault, single/multiple fault simulators, EB tester
Citation:
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida, "Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators," ats, pp.341, Eighth Asian Test Symposium (ATS'99), 1999
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