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Eighth Asian Test Symposium (ATS'99)
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
ASCII Text
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Tsuyoshi Shinogi, Terumine Hayashi, "A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits," Asian Test Symposium, pp. 164, Eighth Asian Test Symposium (ATS'99), 1999.
 
 
BibTex
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@article{ 10.1109/ATS.1999.810746,
author = {Tsuyoshi Shinogi and Terumine Hayashi},
title = {A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits},
journal ={Asian Test Symposium},
volume = {0},
year = {1999},
issn = {1081-7735},
pages = {164},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810746},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits
SN - 1081-7735
SP
EP
A1 - Tsuyoshi Shinogi,
A1 - Terumine Hayashi,
PY - 1999
KW - ATPG
KW - compact test generation
KW - IDDQ testing
KW - parallel processing
VL - 0
JA - Asian Test Symposium
ER -
 
Tsuyoshi Shinogi, Mie University
Terumine Hayashi, Mie University
This paper presents a high performance compact IDDQ test generation system for detecting bridging faults, targeting large circuits. This system is based on the iterative-improvement-based method. We use two-level parallel processing technique for speeding up the test generation significantly, and invoke the assist of a deterministic ATPG for attaining 100% fault efficiency. The experimental results demonstrate its effectiveness.
Index Terms:
ATPG, compact test generation, IDDQ testing, parallel processing
Citation:
Tsuyoshi Shinogi, Terumine Hayashi, "A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits," ats, pp.164, Eighth Asian Test Symposium (ATS'99), 1999
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