A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers

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	Similar Articles Articles by Chanyutt Arjhan Articles by Raghvendra G. Deshmukh

Eighth Asian Test Symposium (ATS'99)

Shanghai, China

November 16-November 18

ISBN: 0-7695-0315-2

	ASCII Text	x
	Chanyutt Arjhan, Raghvendra G. Deshmukh, "A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers," Asian Test Symposium, pp. 127, Eighth Asian Test Symposium (ATS'99), 1999.

	BibTex	x
	@article{ 10.1109/ATS.1999.810740, author = {Chanyutt Arjhan and Raghvendra G. Deshmukh}, title = {A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers}, journal ={Asian Test Symposium}, volume = {0}, year = {1999}, issn = {1081-7735}, pages = {127}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810740}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers SN - 1081-7735 SP EP A1 - Chanyutt Arjhan, A1 - Raghvendra G. Deshmukh, PY - 1999 KW - Parallel multiplier KW - array multiplier KW - parallel divider KW - parallel-array divider KW - pf-model KW - design for testability KW - boundary scan KW - summand-generator KW - summand-counter KW - multiple faults functional testing VL - 0 JA - Asian Test Symposium ER -

Chanyutt Arjhan, Florida Institute of Technology

Raghvendra G. Deshmukh, Florida Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810740

A new fault-detection technique,(-scan, for a specific interconnection of the parallel Braun-multiplier [1,2,3] and the parallel divider [3,4] is presented. The fault-detection model, Pair Faults (pf) [5], and its concept of Multiple Fault Boundaries (MFBs) are generalized with new supporting lemmas. The new technique's application is used to detect all multiple stuck-at faults of the carry save adder (CSA) tree and the adder-subtractor (AS) tree [2,3,4,6] with or without being iterative logic arrays (ILAs) and with or without summand-generator embodiment. Fault location is limited. There are 2(n+2) test patterns to be applied to an n x n CSA tree and its associated test gates and 2(n+4) patterns to an m/n AS tree only.

Index Terms:

Parallel multiplier, array multiplier, parallel divider, parallel-array divider, pf-model, design for testability, boundary scan, summand-generator, summand-counter, multiple faults functional testing

Citation:

Chanyutt Arjhan, Raghvendra G. Deshmukh, "A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers," ats, pp.127, Eighth Asian Test Symposium (ATS'99), 1999

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