Eighth Asian Test Symposium (ATS'99)
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
In this paper, a novel architecture for Built-In Self Test (BIST) and different designs for both the Control and Data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.
Citation:
W. Feng, W.K. Huang, F.J. Meyer, F. Lombardi, "A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD," ats, pp.95, Eighth Asian Test Symposium (ATS'99), 1999