Eighth Asian Test Symposium (ATS'99)
Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
In order to improve the quality of microprocessor tests, the use of instructional sets for testing is indespensable. In this paper; we will present a new method consisting of the automatic generation of a functional test pattern, formed by a combination of instruction sets and enabling the efficient improvement of the fault coverage. With this method, a test pattern is first generated to test all of an S number of instruction mnemonics. Then, for the faults that were undetected by that test pattern, an L number of sets of K numbder of instructions are drawn from the S number of instructions, and the set enabling the efficient improvement of the fault coverage is selected. By repeating this procedure, a high fault coverage can be obtained with a short test pattern. The effectiveness of our method was proved by the results of experiments obtained with the software that was created based on this method.
Citation:
Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki, "Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors," ats, pp.13, Eighth Asian Test Symposium (ATS'99), 1999