loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Seventh Asian Test Symposium (ATS'98)
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination
Singapore
December 02-December 04
ISBN: 0-8186-8277-9
Irith Pomeranz, University of Iowa
W. Kent Fuchs, Purdue University
We propose a procedure for generating test patterns for diagnosis of combinational (or fully-scanned sequential) circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a test pattern to distinguish two faults can be obtained from a test pattern that detects both of the faults by changing the test pattern so as to "undetect" one of the faults, or change the primary outputs on which the faults are detected. The proposed procedure is applied starting from a fault detection test set (a test set that detects every detectable stuck-at fault). For every pair of faults left undistinguished by the test set, the procedure attempts to modify a test pattern that detects both faults such that the resulting, modified pattern would distinguish the faults. We present experimental results to demonstrate the numbers of fault pairs that can be distinguished by the proposed procedure assuming diagnosis based on full responses and diagnosis based on pass/fail information.
Citation:
Irith Pomeranz, W. Kent Fuchs, "A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination," ats, pp.486, Seventh Asian Test Symposium (ATS'98), 1998
Usage of this product signifies your acceptance of the Terms of Use.