Synthesis of Sequential Circuits with Clock Control to Improve Testability

A
ATS
1998
Seventh Asian Test Symposium (ATS'98)
Abstract - Synthesis of Sequential Circuits with Clock Control to Improve Testability

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Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	Kent L. Einspahr, Shashank K. Mehta, Sharad Seth, "Synthesis of Sequential Circuits with Clock Control to Improve Testability," Asian Test Symposium, pp. 472, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741659, author = {Kent L. Einspahr and Shashank K. Mehta and Sharad Seth}, title = {Synthesis of Sequential Circuits with Clock Control to Improve Testability}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {472}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741659}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Synthesis of Sequential Circuits with Clock Control to Improve Testability SN - 1081-7735 SP EP A1 - Kent L. Einspahr, A1 - Shashank K. Mehta, A1 - Sharad Seth, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

Kent L. Einspahr, Concordia University

Shashank K. Mehta, University of Nebraska-Lincoln

Sharad Seth, University of Nebraska-Lincoln

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741659

We propose a new synthesis technique for finite state machines that improves their testability by disabling the clock to a subset of the flip-flops. Distance-matrix results with and without the clock control demonstrate dramatic improvement in the average and worst-case distances between pairs of states. The experimental results using available sequential ATPG tools further verify that the scheme allows significantly shorter tests to be generated with comparable fault coverage.

Citation:

Kent L. Einspahr, Shashank K. Mehta, Sharad Seth, "Synthesis of Sequential Circuits with Clock Control to Improve Testability," ats, pp.472, Seventh Asian Test Symposium (ATS'98), 1998

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