Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA

A
ATS
1998
Seventh Asian Test Symposium (ATS'98)
Abstract - Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA

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Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita, "Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA," Asian Test Symposium, pp. 272, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741624, author = {Noriyoshi Itazaki and Fumiro Matsuki and Yasuyuki Matsumoto and Kozo Kinoshita}, title = {Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {272}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741624}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA SN - 1081-7735 SP EP A1 - Noriyoshi Itazaki, A1 - Fumiro Matsuki, A1 - Yasuyuki Matsumoto, A1 - Kozo Kinoshita, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741624

A new Built-In Self Test (BIST) method for multiple CLB faults of SRAM-Look-Up-Table type FPGA is reported. In this method, self test is performed concurrently for every test block containing eight CLBs. Faulty FPGA which includes up to five faulty CLBs in one test block can be detected completely even if each faulted CLB includes unlimited number of faults.

Citation:

Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita, "Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA," ats, pp.272, Seventh Asian Test Symposium (ATS'98), 1998

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