BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level

A
ATS
1998
Seventh Asian Test Symposium (ATS'98)
Abstract - BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level

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Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	C.-H. Chiang, S.K. Gupta, "BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level," Asian Test Symposium, pp. 244, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741620, author = {C.-H. Chiang and S.K. Gupta}, title = {BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {244}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741620}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level SN - 1081-7735 SP EP A1 - C.-H. Chiang, A1 - S.K. Gupta, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

C.-H. Chiang

S.K. Gupta

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741620

Citation:

C.-H. Chiang, S.K. Gupta, "BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level," ats, pp.244, Seventh Asian Test Symposium (ATS'98), 1998

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