On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates

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	Similar Articles Articles by Teruhiko Yamada Articles by Tsuneto Hanashima Articles by Yasuhiro Suemori Articles by Masaaki Maezawa

Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa, "On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates," Asian Test Symposium, pp. 222, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741617, author = {Teruhiko Yamada and Tsuneto Hanashima and Yasuhiro Suemori and Masaaki Maezawa}, title = {On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {222}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741617}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates SN - 1081-7735 SP EP A1 - Teruhiko Yamada, A1 - Tsuneto Hanashima, A1 - Yasuhiro Suemori, A1 - Masaaki Maezawa, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

Teruhiko Yamada, Meiji University

Tsuneto Hanashima, Meiji University

Yasuhiro Suemori, Meiji University

Masaaki Maezawa, Electrotechnical Laboritories

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741617

We have specified typical fabrication defects of the rapid single-flux-quantum (RSFQ) based logic gates, and then investigated the behavior of defective gates by SPICE simulation to estimate the defect coverage of logic testing. The simulation results show that the logic testing based on the stuck-at fault model can achieve at most 65 % defect coverage for pulse-driven dual-rail RSFQ logic circuits and the defect coverage may increase up to 80 % by properly adding two-pattern tests to the stuck-at fault tests.

Citation:

Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa, "On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates," ats, pp.222, Seventh Asian Test Symposium (ATS'98), 1998

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