An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits

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Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara, "An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits," Asian Test Symposium, pp. 190, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741613, author = {Tomoo Inoue and Toshinori Hosokawa and Takahiro Mihara and Hideo Fujiwara}, title = {An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {190}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741613}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits SN - 1081-7735 SP EP A1 - Tomoo Inoue, A1 - Toshinori Hosokawa, A1 - Takahiro Mihara, A1 - Hideo Fujiwara, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741613

We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We made experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scanwhile preserving almost 100% fault efficiency.

Citation:

Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara, "An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits," ats, pp.190, Seventh Asian Test Symposium (ATS'98), 1998

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