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Seventh Asian Test Symposium (ATS'98)
Fast Window Test Method of Hysteresis Test
Singapore
December 02-December 04
ISBN: 0-8186-8277-9
Conventional method of hysteresis test for digital input pin, as defined by (Vih - Vil), performs two VLS (Voltage Level Search) to measure the actual Vih and Vil. A typical tester spends an average of 120millisec for each VLS, resulting to a test time of 240millisec for each pin requiring Hysteresis test. This paper will introduce a new method which is 70 times faster than the conventional method. The paper presented the test algorithm in pseudo-code format for easy translation to PASCAL, C, FORTRAN, or other language.
Citation:
T. Corpuz, "Fast Window Test Method of Hysteresis Test," ats, pp.179, Seventh Asian Test Symposium (ATS'98), 1998
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