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Seventh Asian Test Symposium (ATS'98)
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation
Singapore
December 02-December 04
ISBN: 0-8186-8277-9
Citation:
K.-J. Lee, J.-J. Tang, W.-Y. Duh, "On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation," ats, pp.113, Seventh Asian Test Symposium (ATS'98), 1998