Test Cycle Count Reduction in a Parallel Scan BIST Environment

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Seventh Asian Test Symposium (ATS'98)

Singapore

December 02-December 04

ISBN: 0-8186-8277-9

	ASCII Text	x
	B. Ayari, P. Varma, "Test Cycle Count Reduction in a Parallel Scan BIST Environment," Asian Test Symposium, pp. 21, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741573, author = {B. Ayari and P. Varma}, title = {Test Cycle Count Reduction in a Parallel Scan BIST Environment}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {21}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741573}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Test Cycle Count Reduction in a Parallel Scan BIST Environment SN - 1081-7735 SP EP A1 - B. Ayari, A1 - P. Varma, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

Citation:

B. Ayari, P. Varma, "Test Cycle Count Reduction in a Parallel Scan BIST Environment," ats, pp.21, Seventh Asian Test Symposium (ATS'98), 1998

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