The industry has accepted IDDQ testing to detect CMOS IC defects. While IDDT testing needs more research to be applicable in practice. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage. This paper presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.