Accelerated Test Points Selection Method for Scan-Based BIST

A
ATS
1997
Sixth Asian Test Symposium (ATS'97)
Abstract - Accelerated Test Points Selection Method for Scan-Based BIST

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Michinobu Nakao Articles by Kazumi Hatayama Articles by Isao Higashi

Sixth Asian Test Symposium (ATS'97)

Akita, JAPAN

November 17-November 18

ISBN: 0-8186-8209-4

	ASCII Text	x
	Michinobu Nakao, Kazumi Hatayama, Isao Higashi, "Accelerated Test Points Selection Method for Scan-Based BIST," Asian Test Symposium, pp. 359, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643983, author = {Michinobu Nakao and Kazumi Hatayama and Isao Higashi}, title = {Accelerated Test Points Selection Method for Scan-Based BIST}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {359}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643983}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Accelerated Test Points Selection Method for Scan-Based BIST SN - 1081-7735 SP EP A1 - Michinobu Nakao, A1 - Kazumi Hatayama, A1 - Isao Higashi, PY - 1997 KW - Test points KW - BIST KW - Testability KW - Optimization VL - 0 JA - Asian Test Symposium ER -

Michinobu Nakao, Hitachi Research Laboratory, Hitachi, Ltd.

Kazumi Hatayama, Hitachi Research Laboratory, Hitachi, Ltd.

Isao Higashi, General Purpose Computer Division, Hitachi, Ltd.,

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643983

This paper presents accelerated test points selection method for circuits designed by full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random patter n testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26k-420k gates).

Index Terms:

Test points, BIST, Testability, Optimization

Citation:

Michinobu Nakao, Kazumi Hatayama, Isao Higashi, "Accelerated Test Points Selection Method for Scan-Based BIST," ats, pp.359, Sixth Asian Test Symposium (ATS'97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.