A Partial Scan Design Method Based on n-Fold Line-up Structures

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	Similar Articles Articles by Toshinori Hosokawa Articles by Toshihiro Hiraoka Articles by Mitsuyasu Ohta Articles by Michiaki Muraoka Articles by Shigeo Kuninobu

Sixth Asian Test Symposium (ATS'97)

Akita, JAPAN

November 17-November 18

ISBN: 0-8186-8209-4

	ASCII Text	x
	Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu, "A Partial Scan Design Method Based on n-Fold Line-up Structures," Asian Test Symposium, pp. 306, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643975, author = {Toshinori Hosokawa and Toshihiro Hiraoka and Mitsuyasu Ohta and Michiaki Muraoka and Shigeo Kuninobu}, title = {A Partial Scan Design Method Based on n-Fold Line-up Structures}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {306}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643975}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A Partial Scan Design Method Based on n-Fold Line-up Structures SN - 1081-7735 SP EP A1 - Toshinori Hosokawa, A1 - Toshihiro Hiraoka, A1 - Mitsuyasu Ohta, A1 - Michiaki Muraoka, A1 - Shigeo Kuninobu, PY - 1997 KW - partial scan KW - n-fold line-up structure KW - dynamic test sequence compaction KW - flip-flop of load/hold type KW - fault efficiency KW - state justification VL - 0 JA - Asian Test Symposium ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643975

Advanced LSI Technology Development Center Matsushita Electric Industrial Co., Ltd. We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structure. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduces the number of test patterns by half.

Index Terms:

partial scan, n-fold line-up structure, dynamic test sequence compaction, flip-flop of load/hold type, fault efficiency, state justification

Citation:

Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu, "A Partial Scan Design Method Based on n-Fold Line-up Structures," ats, pp.306, Sixth Asian Test Symposium (ATS'97), 1997

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