Testing for the programming circuit of LUT-based FPGAs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by H. Michinishi Articles by T. Yokohira Articles by T. Okamoto Articles by T. Inoue Articles by H. Fujiwara

Sixth Asian Test Symposium (ATS'97)

Akita, JAPAN

November 17-November 18

ISBN: 0-8186-8209-4

	ASCII Text	x
	H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara, "Testing for the programming circuit of LUT-based FPGAs," Asian Test Symposium, pp. 242, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643965, author = {H. Michinishi and T. Yokohira and T. Okamoto and T. Inoue and H. Fujiwara}, title = {Testing for the programming circuit of LUT-based FPGAs}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {242}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643965}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Testing for the programming circuit of LUT-based FPGAs SN - 1081-7735 SP EP A1 - H. Michinishi, A1 - T. Yokohira, A1 - T. Okamoto, A1 - T. Inoue, A1 - H. Fujiwara, PY - 1997 KW - shift registers; programming circuit; FPGA; look-up table; shift registers; control circuit; configuration memory cell array; SRAM; fault model VL - 0 JA - Asian Test Symposium ER -

H. Michinishi, Dept. of Inf. Technol., Okayama Univ., Japan

T. Yokohira, Dept. of Inf. Technol., Okayama Univ., Japan

T. Okamoto, Dept. of Inf. Technol., Okayama Univ., Japan

T. Inoue, Dept. of Inf. Technol., Okayama Univ., Japan

H. Fujiwara, Dept. of Inf. Technol., Okayama Univ., Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643965

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

Index Terms:

shift registers; programming circuit; FPGA; look-up table; shift registers; control circuit; configuration memory cell array; SRAM; fault model

Citation:

H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara, "Testing for the programming circuit of LUT-based FPGAs," ats, pp.242, Sixth Asian Test Symposium (ATS'97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.