The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low-cost and easy to use computer-aided-test environment. The ProTest system consists of three parts: an interface to different HDL based CAD-tools, a Computer-Aided-Test tool written in the Java programming language and a low-cost hardware test machine.