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Sixth Asian Test Symposium (ATS'97)
ATREX : Design for Testability System for Mega Gate LSIs
Akita, JAPAN
November 17-November 18
ISBN: 0-8186-8209-4
ASCII Text
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Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi, "ATREX : Design for Testability System for Mega Gate LSIs," Asian Test Symposium, pp. 126, Sixth Asian Test Symposium (ATS'97), 1997.
 
 
BibTex
x
 
@article{ 10.1109/ATS.1997.643947,
author = {Michiaki Emori and Junko Kumagai and Koichi Itaya and Takashi Aikyo and Tomoko Anan and Junichi Niimi},
title = {ATREX : Design for Testability System for Mega Gate LSIs},
journal ={Asian Test Symposium},
volume = {0},
year = {1997},
issn = {1081-7735},
pages = {126},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643947},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - ATREX : Design for Testability System for Mega Gate LSIs
SN - 1081-7735
SP
EP
A1 - Michiaki Emori,
A1 - Junko Kumagai,
A1 - Koichi Itaya,
A1 - Takashi Aikyo,
A1 - Tomoko Anan,
A1 - Junichi Niimi,
PY - 1997
KW - Design for Testabilty
VL - 0
JA - Asian Test Symposium
ER -
 
Michiaki Emori, Fujitsu Limited
Junko Kumagai, Fujitsu Limited
Koichi Itaya, Fujitsu Limited
Takashi Aikyo, Fujitsu Limited
Tomoko Anan, Fujitsu Lsi Tecnology Limited
Junichi Niimi, Fujitsu Lsi Tecnology Limited
We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some example of circuit insertion which is supported by the system.
Index Terms:
Design for Testabilty
Citation:
Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi, "ATREX : Design for Testability System for Mega Gate LSIs," ats, pp.126, Sixth Asian Test Symposium (ATS'97), 1997
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