This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST, are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.