Application of a Design for Delay Testability Approach to High Speed Logic LSIs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by K. Hatayama Articles by M. Ikeda Articles by M. Takakura Articles by S. Uchiyama Articles by Y. Sakamoto

Sixth Asian Test Symposium (ATS'97)

Akita, JAPAN

November 17-November 18

ISBN: 0-8186-8209-4

	ASCII Text	x
	K. Hatayama, M. Ikeda, M. Takakura, S. Uchiyama, Y. Sakamoto, "Application of a Design for Delay Testability Approach to High Speed Logic LSIs," Asian Test Symposium, pp. 112, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643944, author = {K. Hatayama and M. Ikeda and M. Takakura and S. Uchiyama and Y. Sakamoto}, title = {Application of a Design for Delay Testability Approach to High Speed Logic LSIs}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {112}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643944}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Application of a Design for Delay Testability Approach to High Speed Logic LSIs SN - 1081-7735 SP EP A1 - K. Hatayama, A1 - M. Ikeda, A1 - M. Takakura, A1 - S. Uchiyama, A1 - Y. Sakamoto, PY - 1997 KW - Design for Testability KW - Delay Test Generation KW - Delay Testing VL - 0 JA - Asian Test Symposium ER -

K. Hatayama, Hitachi Research Laboratory, Hitachi, Ltd.

M. Ikeda, Hitachi Research Laboratory, Hitachi, Ltd.

M. Takakura, Hitachi Engineering, Co. Ltd.

S. Uchiyama, Hitachi Engineering, Co. Ltd.

Y. Sakamoto, Hitachi Information Technology, Co. Ltd.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643944

This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage combinational circuit model to ordinary combinational circuit model, we add an extra latch, called sub-latch for each scannable flip-flop. A procedure for delay test generation is also developed to establish high fault coverage. The results for a practical application to logic LSIs used in mainframe computers is given to illustrate the effectiveness of our approach.

Index Terms:

Design for Testability, Delay Test Generation, Delay Testing

Citation:

K. Hatayama, M. Ikeda, M. Takakura, S. Uchiyama, Y. Sakamoto, "Application of a Design for Delay Testability Approach to High Speed Logic LSIs," ats, pp.112, Sixth Asian Test Symposium (ATS'97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.