Sixth Asian Test Symposium (ATS'97) Testability Features of R10000 Microprocessor Akita, JAPAN November 17-November 18 ISBN: 0-8186-8209-4
This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus, a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.
Index Terms:
Lfsr, Fault Simulation, Observability Register, Memory Test, Clock Stretch
Citation:
Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok, "Testability Features of R10000 Microprocessor," ats, pp.108, Sixth Asian Test Symposium (ATS'97), 1997 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||