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Sixth Asian Test Symposium (ATS'97)
A concurrent fault-detection scheme for FFT processors
Akita, JAPAN
November 17-November 18
ISBN: 0-8186-8209-4
M. Tsunoyama, Niigata Inst. of Technol., Japan
M. Uenoyama, Niigata Inst. of Technol., Japan
T. Kabasawa, Niigata Inst. of Technol., Japan
This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.
Index Terms:
fast Fourier transforms; concurrent fault-detection; FFT processors; FFT algorithm; reliable real-time systems; fast Fourier transform
Citation:
M. Tsunoyama, M. Uenoyama, T. Kabasawa, "A concurrent fault-detection scheme for FFT processors," ats, pp.94, Sixth Asian Test Symposium (ATS'97), 1997
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