Test generation algorithms are being developed with the continuos creation of incredibly sophisticated computer systems. Although dozen of algorithms have been proposed to cope with these issues, there still remains much to be desired in solving such problems as to determine: which of the existing test generation algorithms could be the most efficient for some particular sequential circuits because different algorithms will be better in different circuits; which testability parameters will have the most or the least influences on test generations so that the designers of circuits can have a global understanding during the designing stage. Testability prediction methodology for sequential circuits using a neural network model has been presented, which a user usually needs for analyzing his/her own circuits and selecting the most suitable test generation algorithm from all the possible algorithms they have, and which a designer for VLSI circuits always needs for making his/her circuits being designed more testable.