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Sixth Asian Test Symposium (ATS'97)
Design of C-Testable Multipliers Based on the Modified Booth Algorithm
Akita, JAPAN
November 17-November 18
ISBN: 0-8186-8209-4
Kwame Osei Boateng, Faculty of Engineering, Ehime University
Hiroshi Takahashi, Faculty of Engineering, Ehime University
Yuzo Takamatsu, Faculty of Engineering, Ehime University
In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns.
Index Terms:
modified Booth Algorithm, multiplier, design for testability, c-testable design, exhaustive testing, cell fault model
Citation:
Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu, "Design of C-Testable Multipliers Based on the Modified Booth Algorithm," ats, pp.42, Sixth Asian Test Symposium (ATS'97), 1997
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