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Sixth Asian Test Symposium (ATS'97)
Automatic Testability Analysis of Boards and MCMs at Chip Level
Akita, JAPAN
November 17-November 18
ISBN: 0-8186-8209-4
ASCII Text
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Marc Perbost, Ludovic Le Lan, Christian Landrault, "Automatic Testability Analysis of Boards and MCMs at Chip Level," Asian Test Symposium, pp. 36, Sixth Asian Test Symposium (ATS'97), 1997.
 
 
BibTex
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@article{ 10.1109/ATS.1997.643913,
author = {Marc Perbost and Ludovic Le Lan and Christian Landrault},
title = {Automatic Testability Analysis of Boards and MCMs at Chip Level},
journal ={Asian Test Symposium},
volume = {0},
year = {1997},
issn = {1081-7735},
pages = {36},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643913},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Automatic Testability Analysis of Boards and MCMs at Chip Level
SN - 1081-7735
SP
EP
A1 - Marc Perbost,
A1 - Ludovic Le Lan,
A1 - Christian Landrault,
PY - 1997
KW - DFT
KW - testability analysis
KW - MCM
VL - 0
JA - Asian Test Symposium
ER -
 
Minimizing the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we pro-pose a testability analysis method for boards and MCMs designed at DASSAULT ELECTRONIQUE. The actual prototype realized according to this new methodology aims at helping testability expert
Index Terms:
DFT, testability analysis, MCM
Citation:
Marc Perbost, Ludovic Le Lan, Christian Landrault, "Automatic Testability Analysis of Boards and MCMs at Chip Level," ats, pp.36, Sixth Asian Test Symposium (ATS'97), 1997
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