Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL

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Sixth Asian Test Symposium (ATS'97)

Akita, JAPAN

November 17-November 18

ISBN: 0-8186-8209-4

	ASCII Text	x
	Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki, "Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL," Asian Test Symposium, pp. 16, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643908, author = {Tsuyoshi Shinogi and Terumine Hayashi and Kazuo Taki}, title = {Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {16}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643908}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL SN - 1081-7735 SP EP A1 - Tsuyoshi Shinogi, A1 - Terumine Hayashi, A1 - Kazuo Taki, PY - 1997 KW - test generation KW - stuck-on fault KW - DFT circuit KW - pass-transistor logic VL - 0 JA - Asian Test Symposium ER -

Tsuyoshi Shinogi, Faculty of Engineering, Mie University

Terumine Hayashi, Faculty of Engineering, Mie University

Kazuo Taki, Faculty of Engineering, Kobe University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643908

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem, we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.

Index Terms:

test generation, stuck-on fault, DFT circuit, pass-transistor logic

Citation:

Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki, "Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL," ats, pp.16, Sixth Asian Test Symposium (ATS'97), 1997

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