A systematic methodology for testability analysis and enhancement of sequential circuit designs using Built-In Self-Test (BIST) is described. Inter-modular test insertions is applied to improve controllability as well as observability in a system level circuit. Circuit partitioning based on functionality has been applied to reduce the computation complexity. The technique is demonstrated on several industrial design circuits for the fax applications. Results show how inter-modular test insertion to enhance testability, guided by testability analysis technique, produce significantly better fault coverage than its original test plan with functional test alone for these industrial circuits. In order to obtain a high fault coverage, functional test, random test and sequential ATPG test have been utilized. We also do test pattern compaction to obtain the minimum size of test pattern. Moreover, very low hardware overhead has been achieved. This methodology has been successfully applied to test system level circuits consisting of sequential circuit modules to do post-design re-synthesis improving overall testability. This methodology has achieved 98% and 99% fault coverage level for several different types of system level circuits from industry.