A new Built-In Self Test (BIST) technique suitable for high performance DSP datapaths is presented. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DP-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan based BIST technique is also presented. We show how DP-BIST can be used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.