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Fifth Asian Test Symposium (ATS'96)
Realistic Linked Memory Cell Array Faults
Hsinchu, TAIWAN
November 20-November 22
ISBN: 0-8186-7478-4
A.J. van de Goor, Delft University of Technology
G.N. Gaydadjiev, Delft University of Technology
The problem of designing memory tests is to establish a relevant set of fault models only consisting of those faults which are shown to be possible to occur in practice. Thereafter, it is a challenge to the test designer to design an optimum test covering the faults of the established fault models. A new fault model, the disturb fault model, is introduced. The notation of linked faults is established and it is shown that march tests can only detect a subset of all linked faults. Thereafter, the universe of linked faults is reduced to the set of realistic linked faults. Last, the effectiveness of the realistic linked fault model is shown via new tests with a higher fault coverage and a shorter test length.
Citation:
A.J. van de Goor, G.N. Gaydadjiev, "Realistic Linked Memory Cell Array Faults," ats, pp.183, Fifth Asian Test Symposium (ATS'96), 1996
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