Formal Verification Of Self-Testing Properties Of Combinational Circuits

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Fifth Asian Test Symposium (ATS'96)

Hsinchu, TAIWAN

November 20-November 22

ISBN: 0-8186-7478-4

	ASCII Text	x
	K. Kawakubo, K. Tanaka, H. Hiraishi, "Formal Verification Of Self-Testing Properties Of Combinational Circuits," Asian Test Symposium, pp. 119, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555147, author = {K. Kawakubo and K. Tanaka and H. Hiraishi}, title = {Formal Verification Of Self-Testing Properties Of Combinational Circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {119}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555147}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Formal Verification Of Self-Testing Properties Of Combinational Circuits SN - 1081-7735 SP EP A1 - K. Kawakubo, A1 - K. Tanaka, A1 - H. Hiraishi, PY - 1996 KW - combinational circuits; combinational circuits; self-testing properties; formal verification; logic function manipulation; satisfiability problem; decision function; characteristic functions; output code words; binary decision diagrams; fault tolerance; self-checking logic; mutiple-input multiple-output circuit; stuck-at faults; Berger code VL - 0 JA - Asian Test Symposium ER -

K. Kawakubo, Fac. of Eng., Fukuyama Univ., Japan

K. Tanaka, Fac. of Eng., Fukuyama Univ., Japan

H. Hiraishi, Fac. of Eng., Fukuyama Univ., Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555147

This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuit's output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method.

Index Terms:

combinational circuits; combinational circuits; self-testing properties; formal verification; logic function manipulation; satisfiability problem; decision function; characteristic functions; output code words; binary decision diagrams; fault tolerance; self-checking logic; mutiple-input multiple-output circuit; stuck-at faults; Berger code

Citation:

K. Kawakubo, K. Tanaka, H. Hiraishi, "Formal Verification Of Self-Testing Properties Of Combinational Circuits," ats, pp.119, Fifth Asian Test Symposium (ATS'96), 1996

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