Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults

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Fifth Asian Test Symposium (ATS'96)

Hsinchu, TAIWAN

November 20-November 22

ISBN: 0-8186-7478-4

	ASCII Text	x
	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai, "Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults," Asian Test Symposium, pp. 100, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555144, author = {Kuen-Jong Lee and Jing-Jou Tang and Tsung-Chu Huang and Cheng-Liang Tsai}, title = {Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {100}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555144}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults SN - 1081-7735 SP EP A1 - Kuen-Jong Lee, A1 - Jing-Jou Tang, A1 - Tsung-Chu Huang, A1 - Cheng-Liang Tsai, PY - 1996 KW - CMOS logic circuits; CMOS bridging faults detection; ATPG system; built-in intermediate voltage sensing; BIFEST system; PODEM-like process; PPSFP-based process; logic monitoring; fault coverage; greedy algorithm; gate threshold ranges; Byzantine General's Command Problem; fault modelling; fault simulation; feedback bridging faults; parallel pattern single fault propagation VL - 0 JA - Asian Test Symposium ER -

Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Jing-Jou Tang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Tsung-Chu Huang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Cheng-Liang Tsai, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555144

This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.

Index Terms:

CMOS logic circuits; CMOS bridging faults detection; ATPG system; built-in intermediate voltage sensing; BIFEST system; PODEM-like process; PPSFP-based process; logic monitoring; fault coverage; greedy algorithm; gate threshold ranges; Byzantine General's Command Problem; fault modelling; fault simulation; feedback bridging faults; parallel pattern single fault propagation

Citation:

Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai, "Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults," ats, pp.100, Fifth Asian Test Symposium (ATS'96), 1996

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