A Test Methodology for Interconnect Structures of LUT-based FPGAs

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	Similar Articles Articles by Hiroyuki Michinishi Articles by Tokumi Yokohira Articles by Takuji Okamoto Articles by Tomoo Inoue Articles by Hideo Fujiwara

Fifth Asian Test Symposium (ATS'96)

Hsinchu, TAIWAN

November 20-November 22

ISBN: 0-8186-7478-4

	ASCII Text	x
	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara, "A Test Methodology for Interconnect Structures of LUT-based FPGAs," Asian Test Symposium, pp. 68, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555139, author = {Hiroyuki Michinishi and Tokumi Yokohira and Takuji Okamoto and Tomoo Inoue and Hideo Fujiwara}, title = {A Test Methodology for Interconnect Structures of LUT-based FPGAs}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {68}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555139}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A Test Methodology for Interconnect Structures of LUT-based FPGAs SN - 1081-7735 SP EP A1 - Hiroyuki Michinishi, A1 - Tokumi Yokohira, A1 - Takuji Okamoto, A1 - Tomoo Inoue, A1 - Hideo Fujiwara, PY - 1996 KW - FPGA KW - Programmable Interconnect Structures KW - Cross Point Switch KW - Configurable Logic Block KW - Test Pattern Generation VL - 0 JA - Asian Test Symposium ER -

Hiroyuki Michinishi, Okayama University

Tokumi Yokohira, Okayama University

Takuji Okamoto, Okayama University

Tomoo Inoue, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555139

In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

Index Terms:

FPGA, Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, Test Pattern Generation

Citation:

Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara, "A Test Methodology for Interconnect Structures of LUT-based FPGAs," ats, pp.68, Fifth Asian Test Symposium (ATS'96), 1996

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