Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors

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	Similar Articles Articles by J.T. van der Linden Articles by M.H. Konijnenburg Articles by A.J. van de Goor

Fifth Asian Test Symposium (ATS'96)

Hsinchu, TAIWAN

November 20-November 22

ISBN: 0-8186-7478-4

	ASCII Text	x
	J.T. van der Linden, M.H. Konijnenburg, A.J. van de Goor, "Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors," Asian Test Symposium, pp. 29, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555132, author = {J.T. van der Linden and M.H. Konijnenburg and A.J. van de Goor}, title = {Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {29}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555132}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors SN - 1081-7735 SP EP A1 - J.T. van der Linden, A1 - M.H. Konijnenburg, A1 - A.J. van de Goor, PY - 1996 VL - 0 JA - Asian Test Symposium ER -

J.T. van der Linden, Delft University of Technology

M.H. Konijnenburg, Delft University of Technology

A.J. van de Goor, Delft University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555132

Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external restrictions and exclusions on test patterns. A cone-oriented circuit partitioning method dealing with these problems is proposed. A serial ATPG scheme for the partitions is proposed. The combined effectiveness is shown by experimental results.

Citation:

J.T. van der Linden, M.H. Konijnenburg, A.J. van de Goor, "Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors," ats, pp.29, Fifth Asian Test Symposium (ATS'96), 1996

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