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Fourth Asian Test Symposium (ATS'95)
DFT for fast testing of self-timed control circuits
Bangalore, India
November 23-November 24
ISBN: 0-8186-7129-7
S. Pagey, Cadence Design Syst. Ltd., Noida, India
A. Khoche, Cadence Design Syst. Ltd., Noida, India
E. Brunvand, Cadence Design Syst. Ltd., Noida, India
In this paper, we present a methodology to perform fast testing of the control path of self-timed circuits. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler (1991). This Compiler translates an OCCAM program description into an interconnection of pre-existing self-timed macro-modules (1989, 1991). The method proposed involves modifying certain modules and structures in such a way that the circuits obtained by translation using these modified modules are testable in above mentioned way.
Index Terms:
asynchronous circuits; fault diagnosis; logic testing; logic CAD; program compilers; automatic test software; design for testability; delays; DFT; fast testing; self-timed control circuits; execution paths; simultaneous testing; OCCAM based circuit compiler; OCCAM program; self-timed macro-modules; translation; modified modules; macromodules
Citation:
S. Pagey, A. Khoche, E. Brunvand, "DFT for fast testing of self-timed control circuits," ats, pp.382, Fourth Asian Test Symposium (ATS'95), 1995
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