Fourth Asian Test Symposium (ATS'95) Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits Bangalore, India November 23-November 24 ISBN: 0-8186-7129-7
This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential machines. This allows the application of arbitrary two-vector test sets necessary for delay fault testing. This arrangement is feasible for practical circuits because today's complex ICs consist, in general, of many sequential machines that may need to be delay testable.
Index Terms:
fault diagnosis; logic testing; sequential circuits; delays; flip-flops; integrated logic circuits; VLSI; logic design; design for testability; flip-flop sharing; standard scan path; delay fault testing; sequential circuits; standard scan path design; two-vector test sets; sequential machines
Citation:
J.P. Hurst, N. Kanopoulos, "Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits," ats, pp.346, Fourth Asian Test Symposium (ATS'95), 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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