Fourth Asian Test Symposium (ATS'95) Functional test generation for path delay faults Bangalore, India November 23-November 24 ISBN: 0-8186-7129-7
We present a novel test generation technique for path delay faults, based on the growth (G) and disappearance (D) faults of programmable logic arrays (PLA). The circuit is modeled as a PLA that is prime and irredundant with respect to every output. Certain tests for G faults, generated by using known efficient methods are transformed into tests for path delay faults. Our algorithm generates tests for all robustly detectable path delay faults in the two-level circuit and its multilevel implementation synthesized using algebraic transformations. Experimental results confirm that the generated vectors, beside robustly covering all path delay faults, also cover most stuck faults in the algebraically factored multilevel circuit. We present some of the best known timings and robust path delay fault coverages for the scan/hold versions of several ISCAS89 circuits, for which the PLA description could be obtained.
Index Terms:
programmable logic arrays; delays; multivalued logic; fault location; fault diagnosis; logic testing; functional test generation; path delay faults; programmable logic arrays; PLA; growth faults; disappearance faults; robustly detectable path delay faults; two-level circuit; algebraic transformations; generated vectors; stuck faults; algebraically factored multilevel circuit; timings; fault coverages; scan/hold versions; ISCAS89 circuits
Citation:
M.K. Srinivas, V.D. Agrawal, M.L. Bushnell, "Functional test generation for path delay faults," ats, pp.339, Fourth Asian Test Symposium (ATS'95), 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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